1. Field of the Invention
The present invention relates to an apparatus for correcting a phase error in a sampling signal suited for use in such process as velocity error correction, sampling phase control, and hue control for a video signal constituted as a digital signal, for example, in a video tape recorder (VTR).
2. Description of the Prior Art
There has so far been known a system as shown in FIG. 1, for example, used as a velocity error correcting circuit in a VTR, in which a read phase of a reproduced video sampling signal stored in a main memory 1 is phase modulated by a phase error signal SVE formed of a velocity error signal, whereby a time base correction is given to the velocity error included in a reproduced video signal VDIN. The method for correcting velocity error by means of phase modulation is disclosed in the Japanese magazine "Broadcasting Technology", August, 1975, pages 571-578.
Referring to FIG. 1, a reproduced video signal VDIN is converted into, for example, 910 samples of digital data for each H period in an analog to digital converting circuit 2 according to a sampling signal SSM1 supplied from a write clock generating circuit 3, and the sampled digital data DSM are successively written in a main memory 1 as a write clock pulse PWT generated by the write clock generating circuit 3 is supplied through a sequencer 4 to the main memory 1.
These data written in the main memory 1 are read out according to a read clock pulse PRD generated by a read clock generating circuit 6 through a drop-out compensating circuit 5, and these read out sampled data DRO are supplied to a digital to analog converting circuit 7. The sampled data DRO is converted by the digital to analog converting circuit 7 into an analog video signal VDMI according to a clock pulse signal SSM2 synchronized with the read clock pulse PRD, and the signal VDMI is output as an output video signal VDOUT after having added thereto a reference synchronizing signal SYNC1 etc. in a processor 8.
The reference synchronizing signal SYNC1, as well as a synchronizing signal SYNC2 for the read clock generating circuit 6, is generated in a synchronizing signal generating circuit 9 based upon a reference video signal VDREF and a broadcast synchronizing signal SYNCREF.
In the conventional arrangement as shown in FIG. 1, when the phase .theta. of the reproduced video signal VDIN deviates as shown in FIG. 2 (A), velocity errors (.theta. 1H-.theta. OH), (.theta. 2H-.theta. 1H), . . . are detected by the write clock generating circuit 3 based on the horizontal synchronizing signal at intervals of its period H at time points t0H, t1H, t2H, . . . The write clock generating circuit 3 supplies the read clock generating circuit 6 with the phase error signal SVE (FIG. 2 (B)) which is formed by assigning, for example, linearly increasing phase error data .DELTA. .theta. 1, .DELTA. .theta. 2, .DELTA. .theta. 3, .DELTA. .theta. 4, . . . to the sampling time points t01, t02, t03, t04, . . . assuming that the velocity error detected at an interval of one H period is, for example, linearly varying during the corresponding one H period.
The read clock generating circuit 6 applies a phase modulation to the read clock pulse PRD in such a way that the generated phases of the read clock pulse PRD are shifted (i.e., advanced or delayed) the phase correction data .DELTA. .theta. 1, .DELTA. .theta. 2, .DELTA. .theta. 3, . . . at the sampling time points t01, t02, t03, . . . within the one H period, and thus the analog video signal VDMI in which the velocity error has been corrected is obtained by reading the sampled data D01, D02, D03, . . . of the reproduced video signal VDIn (FIG. 3 (A)) written in the main memory 1 at the time points which are shifted from the time points in accordance with the predetermined sampling period by the phase correction data .DELTA. .theta. 1, .DELTA. .theta. 2, .DELTA. .theta. 3, . . . as shown in FIG. 3 (B).
However, when the read clock pulse PRD is phase modulated by the phase error signal SVE as in the case of FIG. 1, the velocity error is removed only after the digital DRO has been converted into the analog signal VDMI in the digital to analog converting circuit 7.
On reflection, it may be realized that the sampled data D01, D02, D03, . . . are corrected and become significant when the time points for reading them out are phase modulated. But, if such discrete sampled data were delivered to a digital processing circuit in the rear stage, of the apparatus the data which would have been made free from velocity error by virtue of the phase modulation with the phase error signal SVE would be in effect turned back into the digital sampled signal including the original velocity error by being restored samples at a predetermined period since the digital processing circuit in the rear stage is structured so as to process the sampled data with a specific clock signal having the predetermined period.
Therefore, if it is intended to supply such a discrete digital sampled signal to the digital processing circuit in the rear stage while using the conventional structure as shown in FIG. 1, the video output VDMI of the digital to analog converting circuit 7 must be converted once again into a digital sampled signal by the use of a separate analog to digital converting circuit, which will make the structure larger in scale and more complex and unavoidably invite deterioration in the characteristic of the sampled signal.